1. Field of the Invention
The present invention relates to a semiconductor structure. More particularly, it relates to a strained-channel semiconductor structure and method of fabricating the same.
2. Description of the Related Art
Size reduction of the metal-oxide-semiconductor field-effect transistor (MOSFET), including reduction of gate length and gate oxide thickness, has enabled continuous improvement in performance, reduced density, and cost per unit of integrated circuits.
In order to further enhance transistor performance, strain can be introduced in the transistor channel to improve carrier mobility and device scaling. There are several existing approaches to introducing strain in a transistor channel region.
In one conventional approach, as described in the paper entitled “NMOS and PMOS transistors fabricated in strained silicon/relaxed silicon-germanium structures”, by J. Welser et al., published at the December 1992 International Electron Devices Meeting held in San Francisco, Calif., pp. 1000-1002, a relaxed silicon germanium (SiGe) buffer layer 110 is provided beneath channel region 126, as shown in FIG. 1A.
In FIG. 1B and FIG. 1C, a simple model of different lattice constants is used to show the intersection between relaxed SiGe layer 114 of buffer layer 110 and strained-Si layer 130. In FIG. 1B, model 135 shows the natural lattice constant of Si, smaller than that of SiGe shown by model 115. In FIG. 1C, when a thin layer of epitaxial Si (model 135) is grown on the relaxed SiGe layer 114 (model 115), unit cell 136 of Si shown in model 135 is subject to biaxial tensile strain by lateral stretching. The thin layer of epitaxial Si becomes strained-Si layer 130 shown in FIG. 1A.
In FIG. 1A, a transistor formed on the epitaxial strained-Si layer 130 has a channel region 126 under biaxial tensile strain. In this approach, relaxed SiGe layer 114 is a stressor that introduces strain in channel region 126. The stressor, in this case, is placed below channel region 126. Significant mobility enhancement has been reported for both electrons and holes in bulk transistors using a silicon channel under biaxial tensile strain. In the aforementioned approach, the epitaxial silicon layer 130 is strained before forming the transistor.
Hence, there are concerns about possible strain relaxation resulting from subsequent high temperature CMOS processes. Further, the approach is very expensive as the SiGe buffer layer 110 with a thickness on the order of micrometers must be grown. Numerous dislocations exist in relaxed SiGe layer 114, some of which propagate to the strained-Si layer 130, resulting in high defect density, thereby negatively affecting transistor performance.
Moreover, another approach is disclosed in U.S. patent application No. 2003/0080361 by A. Murthy et. al., entitled “Semiconductor transistor having a stressed channel”, and an approach with strain in a channel region by stressors disposed on adjacent sides of the channel region is introduced.
In addition, a pMOSFET with a SiGe source/drain and a SiGe quantum well channel is described in detail in a paper disclosed by Ouyang et. al., entitled “Two-dimensional bandgap engineering in a novel Si/SiGe PMOSFET with enhanced device performance and scalability”, published in pp. 151-154 of the Simulation of Semiconductor Processes and Devices (SISPAD).
In FIG. 2, the cross section of the semiconductor transistor with a gate structure G is shown and the elements of the gate stack 203 thereof are omitted for simplicity. In FIG. 2, the gate stack 203 is disposed over the surface of a semiconductor substrate, for example a silicon substrate 200, between two isolation regions 202 formed in the silicon substrate 200. In addition, two doped regions 204a and 204b are disposed in the silicon substrate 200 between the isolation regions 202 and located on opposing sides of the gate stack 203. A channel region 208 is further formed in the silicon substrate 200 between the doped regions 204a and 204b. Films 206a and 206b including silicon, germanium and boron are epitaxially formed in the respective region above the doped regions 204a and 204b disposed on opposing sides of the gate stack 203 and act as stressors.
In such a semiconductor transistor, the outer sidewall of the film 206a or 206b corresponding to the channel region 208 entirely contacts the adjacent isolation region 202 and the strain caused by each stressor (referring to the film 206a and the film 206b) to the channel region 208 is partially buffered by the adjacent isolation region 202 thereof such that the magnitude of a strain in the channel region 208 is not optimized and can thus be reduced.
Photon area 210 in FIG. 2 is further enlarged and shown in FIG. 3 to illustrate the atomic arrangement of the isolation region 202 and portions of the channel region (referring to the doped region 204a and the adjacent channel region 208) adjacent to the stressor (referring to the film 206a) therein. At this point, the doped region 204a comprises the same material as the silicon substrate 200 and the atomic arrangement thereof is an atomic arrangement of silicon atoms 210, having a lattice constant in nature. In the film 206a, the atomic arrangement is an atomic arrangement of material such as epitaxially formed silicon germanium (SiGe) 212 here, having another lattice constant in nature greater than that of silicon atoms 210 of the adjacent doped region 204a. 
In addition, the film 206a also contacts the isolation region 202 on the left side. The isolation regions 202 are usually filled with the amorphous material such as silicon oxide 214 and a hetero-junction of proper atomic arrangements cannot be constituted between the amorphous material of the isolation region 202 and the film 206a. Thus, the amorphous material, for example silicon oxide 214, in the isolation region 202 does not force the atoms of material of the stressor to be arranged in any specific way.
Further, the silicon oxide 214 filled in the isolation region 202 has a smaller Young's modulus (about 69 GPa) than that of the silicon material (about 170 GPa) in the channel region (referring to the doped region 204a and the channel region 208) and results in a lager strain under a fixed stress. Thus, the isolation region 202 filled with silicon oxide is more compressive or stretchable than the channel region of the silicon material and the magnitude of a strain in the channel region 208 close to the doped region 204a provided by the stressor (referring to the film 206a here) can be partially buffered by the silicon oxide of the adjacent isolation region 202 such that the strain in the channel region 208 is not optimized and can thus be reduced.
Thus, the present invention provides a strained-channel semiconductor structure to enhance the strain in the channel region by improving the location and design of the stressors therein.